Xilinx Field Programmable Gate Array, Part #: XCR3384XL-10TQG144I is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the CoolRunner XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the CoolRunner XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. CoolRunner devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.

Features

• Fast Zero Power (FZP) design technique provides ultra-low power and very high speed

• Innovative CoolRunner™ XPLA3 architecture combines high speed with extreme flexibility

• Based on industry’s first TotalCMOS PLD — both CMOS design and process technologies

• Advanced 0.35μ five layer metal EEPROM process

• 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface

• Support for complex asynchronous clocking

• Excellent pin retention during design changes

XLX:XCR3384XL-10TQG144I

XCR3384XL-10TQG144I